First-in-first-out (FIFO) storage devices are used in processors and communications applications involving transfers of data between different domains, commonly where the domains may operate at different data rates. While the data rates differ, and often vary, between the domains, the signals between them may be clocked relative to the same fundamental clock frequency (i.e., synchronous) or clocked relative to different fundamental clock frequencies (i.e., asynchronous). In a synchronous application, the buffering provided by the FIFO compensates for differences in the data rates of the two domains. In an asynchronous application, the buffering provided by the FIFO compensates for differences in the both the data rates and the clock frequencies of the two domains. In either case, the buffering helps to avoid data loss due to transfer of data at times or speeds when the receiving domain can not handle it and/or to avoid data duplication because the receiving domain is expecting and ready to receive additional data while the sending domain is still transferring prior data.
Most FIFO implementations, however, are limited by the finite size or depth of the memory or register array implementing the FIFO buffer. For example, data may still be lost if the sending domain sends more data when the FIFO storage device is already full of data awaiting transfer to the sink in the receiving domain. Various techniques have been developed to feed information about the fill level and/or write status of the FIFO, from the receiving or sink domain to the sending or source domain. However, need for further improvement in such techniques remains.